Amiga 500 2MB FAST Ram Expansion

01_parts

Introduction:

Having recently got myself an Amiga 500 I had run out of things that I could do to enhance it. There was full motherboard re-capping, keyboard re-capping , ‘OCD’ level cleaning of the unit and all peripherals, a PSU Re-Cap, and the AMRAM1M5 Memory Expansion clean-up. What was next..?

I briefly thought about throwing together some sort of Fast RAM thing but quit that idea when I thought of all that DRAM complexity and the Refresh circuitry needed. It would be a lot simpler using SRAM if that was possible.

I took a look at the 68K Edge Connector pinouts and discovered no DRAMΒ  RAS or CAS related stuff there at all. A quick look at the 68000 datasheet showed that all I need is a few of the control signals on the CPU bus to get something going!

I already had a couple of 1024 x8 SRAM ICs spare in a box – if I could get two of these to appear as 16Bit wide data then those would do the job. Throw in a bit of address decoding and they should appear in the Fast RAM memory map at $200000 thru $3FFFFF.

The simplest way to assemble this would be to build it on top of a spare 68000 CPU. All the signals needed could be linked to the pins of the IC so no messy wires needed to run to the motherboard. Throw in a removable Jumper and the Fast RAM could be disabled if needed.

Game On!

02_sram_wired

The two 1024KB SRAMS were mounted on top of each other with all the common signals linked at the IC legs to cut down the total number of wires needed. All the Addresses were commoned along with /OE, R_/W and CE2. VCC & GND are also shared with a 330nF ceramic cap linked in. The leads were encapsulated with Loctite so prevent any breaking off when formed & trimmed.

Mount up!

03_sram_mounted_on_68k

Here the SRAM ICs are mounted on top of the 68000 with a piece of foam double-sided tape keeping them in place. The single unconnected wire is the CE2 signal that activates the SRAMS – we need some extra ICs to activate this when the CPU looks inside the first 2MB of Fast RAM at addresses $200000 thru $3FFFFF.

Decode Me Baby

05_finished_01

By using a 74HC138 and single-gate inverter the address decoding was done. The HC138 looks at the 68000 address A21, A22, and A23. If A21 goes HIGH and A22 + A23 are LOW then we know that the CPU is looking inside the range $200000 thru $3FFFFF. The HC138 ouput Y1 goes LOW when this is true. Our SRAM’s CE2 signal needs to be HIGH to activate so a single-gate inverter was used to flip this over.

The jumper was added to the SRAM side of the CE2 signal. With the jumper removed the decoded signal is disconnected and CE2 is pulled LOW by a 47K resistor to keep the memory inactive. Placing the jumper lets the decode signal through and the memory comes alive.

Get in there!

07_installled_enabled

With the modified 68000 in place it was time to power-on! The mod is low-profile so it does not sit against the metal cover when the unit is re-assembled.

This type of memory is not the Amiga Auto-Config type. This means the Amiga needs to be told it is there or it will never be used. Luckily we have AutoAddRAM to sniff the Fast RAM memory locations and automatically add it to the memory pool:17_wb_startup

When AutoAddRAM detects the extra memory the decoder kicks in and the SRAM is activated as seen on the ‘scope:09_decoded_on_scope

Go Workbench!

Workbench has detected the extra RAM in the Fast section. My A500 has an AMRAM1M5 trapdoor expansion so the total Fast reported is 3.5MB19_wb_avail

SYSINFO Speed TESTS!

Without the Fast RAM it shows 552 Dhrystones:15_speed-standard

With the Fast RAM activated we get 728 Dhrystones –Β  along with the “Now we are talkin” message of encouragement πŸ˜‰16_speed_fastram

The ‘Post-IT’ Schematic

20_post-it_schematic

This really shows how simple this project is. Just a few control signals are needed to get it up and running!

** March 2017 Update **

After running Keir Fraser’s SysTest test application I found that the memory test was failing during the Checkerboard test routines. These routines write patterns of bytes like OxOOOOFFFF & OxFFFFOOOO and reads them back to verify the memory cells.

During this test the GND and VCC rails are heavily loaded and the little wires I used were not up to the job. The voltage differerence between the CPU pin GND and the memory IC GND was about a volt either way during the test. This needed a bit of beefing-up.

I added thicker wires from the CPU GND & VCC pins from both sides and looped them through to the memory and decoder circuits. The voltage difference was now down to about 150mV during the test.21_better-vcc-gnd

The memory test is now a lot healther. No errors reported after 34 tests πŸ™‚

22_ram_test

// END

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